Altera Transceiver PHY IP Core User Manual
Page 255
The following table describes the options available on the Additional Options tab:
Table 10-5: Additional Options
Name
Value
Description
Enable tx_coreclkin
On/Off
When you turn this option on,
tx_coreclkin
connects to the write clock of the TX phase
compensation FIFO and you can clock the
parallel TX data generated in the FPGA fabric
using this port. This port allows you to clock the
write side of the TX phase compensation FIFO
with a user-provided clock, either the FPGA
fabric clock, the FPGA fabric-TX interface clock,
or the input reference clock. You must turn this
option On when the FPGA fabric transceiver
interface width:PCS-PMA interface width is
50:40 or when you specify the 10G datapath with
a fabric transceiver interface width:PCS-PMA
interface width of 64:32.
For the GT datapath, if you are using different
reference clock pins for the TX and RX channels,
you must instantiate two separate Low Latency
PHY IP Core instances for TX and RX channels.
The reference clock pins for each channel must
reside in the same transceiver bank.
For more information refer to the “FPGA Fabric-
Transceiver Interface Clocking” section in the
Stratix V Transceiver Clocking chapter.
Enable rx_coreclkin
On/Off
When you turn this option on,
rx_coreclkin
connects to the read clock of the RX phase
compensation FIFO and you can clock the
parallel RX output data using
rx_coreclk
. This
port allows you to clock the read side of the RX
phase compensation FIFO with a userprovided
clock, either the FPGA fabric clock, the FPGA
fabric RX interface clock, or the input reference
clock. rx_coreclkin is not available for the GT
datapath.
You must turn this option On when the FPGA
fabric transceiver interface width:PCS-PMA
Interface width is 50:40 or when you specify the
10G datapath with a fabric transceiver interface
width:PCS-PMA Interface width of 64:32.
For more information refer to the “FPGA Fabric-
Transceiver Interface Clocking” section in the
Stratix V Transceiver Clocking chapter.
10-8
Additional Options Parameters
UG-01080
2015.01.19
Altera Corporation
Low Latency PHY IP Core