Altera Transceiver PHY IP Core - Manual (Page 477)

Name Dir Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
Rx_10g_fifo_insert
[-1:0]
Output Yes Active-high 10G BaseR RX FIFO insertion flag
When asserted, indicates that a word has been
inserted into the TX FIFO. This signal is used for
the 10GBASE-R protocol.
CRC32
rx_10g_crc32err
[-1:0]
Output No For the Interlaken protocol, asserted to indicate
that the CRC32 Checker has found a CRC32 error
in the current metaframe. Is is asserted at the end
of current metaframe. This signal is
pulse-stretched; you must use a synchronizer.
Frame Generator
tx_10g_diag_status
[2-1:0]
Input No For the Interlaken protocol, provides diagnostic
status information reflecting the lane status
message contained in the Framing Layer
Diagnostic Word (bits[33:32]). This message is
inserted into the next Diagnostic Word generated
by the Frame Generation Block. The message must
be held static for 5 cycles before and 5 cycles after
the tx_frame pulse.
tx_10g_burst_en
[-1:0]
Input No For the Interlaken protocol, controls frame
generator reads from the TX FIFO. Latched once
at the beginning of each metaframe.When 0, the
frame generator inserts SKIPs. When 1, the frame
generator reads data from the TX FIFO. Must be
held static for 5 cycles before and 5 cycles after the
tx_frame
pulse.
tx_10g_frame
[-1:0]
Output No For the Interlaken protocol, asserted to indicate
the beginning of a new metaframe inside the frame
generator. This signal is pulse-stretched; you must
use a synchronizer.
Frame Synchronizer
rx_10g_frame
[-1:0]
Output No For the Interlaken protocol, asserted to indicate
the beginning of a new metaframe inside the frame
synchronizer. This signal is pulse-stretched, you
must use a synchronizer. This signal is
pulse-stretched; you must use a synchronizer.
14-66 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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