Analog settings for arria v gz devices, Xcvr_io_pin_termination, Analog settings for arria v gz devices -11 – Altera Transceiver PHY IP Core User Manual
Page 605
Description
When set to
DYNAMIC_CTL
, the PCS block controls the V
OD
and pre-emphasis coefficients for PCI
Express. When this assignment is set to
RAM_CTL
the V
OD
and pre-emphasis are controlled by other
assignments, such as
XCVR_TX_PRE_EMP_1ST_POST_TAP
.
Options
• DYNAMIC_CTL: for PCI Express
• RAM_CTL: for all other protocols
Assign To
Pin - TX serial data
Analog Settings for Arria V GZ Devices
Analog Settings for Arria V GZ Devices
This section lists the analog parameters for Arria V GZ devices whose original values are place holders for
the values that match your electrical board specification. In the following table, the default value of an
analog parameter is shown in bold type. The parameters are listed in alphabetical order.
The following table lists the analog parameters with global or computed default values. You may want to
optimize some of these settings. The default value is shown in bold type. For computed analog
parameters, the default value listed is for the initial setting, not the recomputed setting. The parameters
are listed in alphabetical order.
For more information about the Pin Planner, refer to About the Pin Planner in Quartus II Help. For more
information about the Assignment Editor, refer to About the Assignment Editor in Quartus II Help.
For more information about Quartus II Settings, refer to Quartus II Settings File Manual.
Related Information
•
•
•
•
•
XCVR_IO_PIN_TERMINATION
Pin Planner and Assignment Editor Name
Transceiver I/O Pin Termination
Description
Specifies the intended on-chip termination value for the specified transceiver pin. Use External Resistor if
you intend to use off-chip termination.
UG-01080
2015.01.19
Analog Settings for Arria V GZ Devices
19-11
Analog Parameters Set Using QSF Assignments
Altera Corporation