10g pcs pattern generators – Altera Transceiver PHY IP Core User Manual
Page 340
Parameter
Range
Description
Enable TX data bitslip
On/Off
When you turn this option On, the TX
gearbox operates in bitslip mode.
Enable RX data polarity inversion
On/Off
When you turn this option On, the
gearbox inverts the polarity of RX data
allowing you to correct incorrect
placement and routing on the PCB.
Enable RX data bitslip
On/Off
When you turn this option On, the 10G
PCS RX block synchronizer operates in
bitslip mode.
Enable tx_10g_bitslip port
On/Off
When you turn this option On, the 10G
PCS includes the
tx_10g_bitslip
input
port. The data slips 1 bit for every
positive edge of the
tx_10g_bitslip
input. The maximum shift is <
pcswidth> -1 bits, so that if the PCS is 64
bits wide, you can shift 0-63 bits.
Enable rx_10g_bitslip port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_bitslip
input
port. The data slips 1 bit for every
positive edge of the
rx_10g_bitslip
input. he maximum shift is < pcswidth>
-1 bits, so that if the PCS is 64 bits wide,
you can shift 0-63 bits.
PRBS Verifier
You can use the PRBS pattern generators for verification or diagnostics. The pattern generator blocks
support the following patterns:
• Pseudo-random binary sequence (PRBS)
• Pseudo-random pattern
• Square wave
Table 12-35: PRBS Parameters
Parameter
Range
Description
Enable rx_10g_prbs ports
On/Off
When you turn this option On, the PCS
includes the
rx_10g_prbs_done
,
rx_10g_
prbs_err
and
rx_10g_prbs_err_clr
signals
to provide status on PRBS operation.
Related Information
10G PCS Pattern Generators
The 10G PCS supports the PRBS, pseudo-random pattern, and square wave pattern generators. You
enable the pattern generator or verifiers in the 10G PCS, by writing a 1 to the
TX Test Enable
and
RX
12-42
10G PCS Pattern Generators
UG-01080
2015.01.19
Altera Corporation
Stratix V Transceiver Native PHY IP Core