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1g/10gbe phy state machine logic requirements, Editing a 1g/10gbe mif file, 1g/10gbe phy state machine logic requirements -23 – Altera Transceiver PHY IP Core User Manual

Page 132: Editing a 1g/10gbe mif file -23, 1g/10gbe, Phy state machine logic requirements

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• Channel number—specifies the requested channel

• Mode—specifies 1G or 10G mode for the corresponding channel

2. Select a channel for reconfiguration and send an ack/busy signal to the requestor. The requestor

should deassert its request signal when the ack/busy is received.

3. Pass the selected channel and rate information to the state machine for processing.

4. Wait for a done signal from the state machine indicating that the reconfiguration process is complete

and it is ready to service another request.

1G/10GbE PHY State Machine Logic Requirements

The state machine should implement the following logic. You can modify this logic based on your system

requirements:
1. Wait for

reconfig_busy

from the Transceiver Reconfiguration Controller to be deasserted and the

tx_ready

and

rx_ready

signals from the Transceiver PHY Reset Controller to be asserted. These

conditions indicate that the system is ready to service a reconfiguration request.

2. Set the appropriate channel for reconfiguration.

3. Initiate the MIF streaming process. The state machine should also select the appropriate MIF (stored

in the ROMs) to stream based on the requested mode.

4. Wait for the

reconfig_busy

signal from the Transceiver Reconfiguration Controller to assert and

then deassert indicating the reconfiguration process is complete.

5. Toggle the digital resets for the reconfigured channel and wait for the link to be ready.

6. Deassert the

ack/busy

signal for the selected channel. Deassertion of

ack/busy

indicates to the arbiter

that the reconfiguration process is complete and the system is ready to service another request.

Editing a 1G/10GbE MIF File

This topic shows how to edit a 1G/10GbE MIF file to change between 1G and 10Gb Ethernet.
The MIF format contains all bit settings for the transceiver PMA and PCS. Because the 1G/10GbE PHY IP

Core only requires PCS reconfiguration for a rate change, the PMA settings should not change. Removing

the PMA settings from the MIF file also prevents an unintended overwrite of PMA parameters set

through other assignments. A few simple edits to the MIF file removes the PMA settings. Complete the

following steps to edit the MIF file:

1. Replace line 17 with

"13: 0001000000010110; -- PMA - RX changed to removed CTLE".

2. Replace line 20 with

"16: 0010100000011001; -- PMA - RX continued".

3. Replace line 4 with

"4: 0001000000000000; -- PMA - TX"

.

4. Remove lines 7-10. These lines contain the TX settings (V

OD

, post-tap, pre-tap).

5. Renumber the lines starting with the old line 11.

6. Change the depth at the top of the file from 168 to 164.

UG-01080

2015.01.19

1G/10GbE PHY State Machine Logic Requirements

5-23

1G/10 Gbps Ethernet PHY IP Core

Altera Corporation

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