Cyclone v transceiver native phy ip core overview – Altera Transceiver PHY IP Core User Manual
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Cyclone V Transceiver Native PHY IP Core
Overview
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2015.01.19
UG-01080
The Cyclone V Transceiver Native PHY IP Core provides direct access to all control and status signals of
the transceiver channels. Unlike other PHY IP Cores, the Native PHY IP Core does not include an Avalon
Memory-Mapped (Avalon-MM) interface. Instead, it exposes all signals directly as ports. The Cyclone V
Transceiver Native PHY IP Core includes the Standard PCS. You can select the PCS functions and control
and status port that your transceiver PHY requires.
The Native Transceiver PHY does not include an embedded reset controller. You can either design
custom reset logic or incorporate Altera’s “Transceiver PHY Reset Controller IP Core” to implement reset
functionality.
As the following figure illustrates, TX PLL and clock data recovery (CDR) reference clocks from the pins
of the device are input to the PLL module and CDR logic. The Standard PCS drives TX parallel data and
receives RX parallel data.
Figure 15-1: Cyclone Native Transceiver PHY IP Core
PLLs
PMA
altera _xcvr_native_cv
Transceiver Native PHY
RX PCS Parallel Data
TX PCS Parallel Data
CDR Reference Clock
TX PLL Reference Clock
CDR
RX Serial Data
to
FPGA fabric
Transceiver
Reconfiguration
Controller
Reconfiguration to XCVR
Reconfiguration from XCVR
TX and RX Resets
Calilbration Busy
PLL and RX Locked
Transceiver
PHY Reset
Controller
TX Serial Data
Serializer
De-
Serializer
Standard
PCS
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