Altera Transceiver PHY IP Core - Manual (Page 126)

Table 5-15: PMA Registers - TX and RX Serial Data Interface
The following PMA registers allow you to customize the TX and RX serial data interface
Address Bit R/W Name Description
0xA8
0 RW
tx_invpolarity
When set to 1, the TX interface inverts the polarity of the
TX data. Inverted TX data is output from the 8B/10B
encoder.
1 RW
rx_invpolarity
When set to 1, the RX channels inverts the polarity of the
received data. Inverted RX data is input to the 8B/10B
decoder.
2 RW
rx_bitreversal_enable
When set to 1, enables bit reversal on the RX interface.
The RX data is input to the word aligner.
3 RW
rx_bytereversal_
enable
When set, enables byte reversal on the RX interface. The
RX data is input to the byte deserializer.
4 RW
force_electrical_idle
When set to 1, forces the TX outputs to electrical idle.
0xA9
0 R
rx_syncstatus
When set to 1, indicates that the word aligner is
synchronized to incoming data.
1 R
rx_patterndetect
When set to 1, indicates the 1G word aligner has detected
a comma.
2 R
rx_rlv
When set to 1, indicates a run length violation.
3 R
rx_rmfifodatainserted
When set to 1, indicates the rate match FIFO inserted
code group.
4 R
rx_rmfifodatadeleted
When set to 1, indicates that rate match FIFO deleted
code group.
5 R
rx_disperr
When set to 1, indicates an RX 8B/10B disparity error.
6 R
rx_errdetect
When set to 1, indicates an RX 8B/10B error detected.
PCS Registers
These registers provide PCS status information.
Table 5-16: PCS Registers
Addr Bit Acce
ss
Name Description
0x80 31:0 RW
Indirect_addr
Because the PHY implements a single channel, this
register must remain at the default value of 0 to specify
logical channel 0.
0x81
2 RW
RCLR_ERRBLK_CNT
Error Block Counter clear register. When set to 1, clears
the
RCLR_ERRBLK_CNT
register. When set to 0, normal
operation continues.
3 RW
RCLR_BER_COUNT
BER Counter clear register. When set to 1, clears the
RCLR_BER_COUNT
register. When set to 0, normal
operation continues.
UG-01080
2015.01.19
PCS Registers 5-17
1G/10 Gbps Ethernet PHY IP Core Altera Corporation
Send Feedback