Altera Transceiver PHY IP Core - Manual (Page 23)

MegaWizard Plug-In Manager Flow
This section describes how to specify parameters and simulate your IP core with the MegaWizard Plug-In
Manager.
The MegaWizard
™ Plug-In Manager flow allows you to customize your IP core and manually integrate
the function into your design.
Specifying Parameters
To specify IP core parameters, follow these steps:
1. Create a Quartus II project using the New Project Wizard available from the File menu.
2. In the Quartus II software, launch the IP Catalog.
3. You can select the IP core for your protocol implementation from the IP Catalog.
4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these
parameters, refer to the "Parameter Settings" chapter in this document or the "Documentation" button
in the MegaWizard parameter editor.
Note: Some IP cores provide preset parameters for specific applications. If you wish to use preset
parameters, click the arrow to expand the Presets list, select the desired preset, and then click
Apply. To modify preset settings, in a text editor modify the /ip/altera/
alt_mem_if_interfaces/alt_mem_if__emif/
alt_mem_if__mem_model.qprs file.
5. If the IP core provides a simulation model, specify appropriate options in the wizard to generate a
simulation model.
Note: Altera IP supports a variety of simulation models, including simulation-specific IP functional
simulation models and encrypted RTL models, and plain text RTL models. These are all
cycle-accurate models. The models allow for fast functional simulation of your IP core instance
using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text
RTL model is generated, and you can simulate that model.
Note: For more information about functional simulation models for Altera IP cores, refer to
Simulating Altera Designs in volume 3 of the Quartus II Handbook.
Caution: Use the simulation models only for simulation and not for synthesis or any other purposes.
Using these models for synthesis creates a nonfunctional design.
6. If the parameter editor includes EDA and Summary tabs, follow these steps:
a. Some third-party synthesis tools can use a netlist that contains the structure of an IP core but no
detailed logic to optimize timing and performance of the design containing it. To use this feature if
your synthesis tool and IP core support it, turn on Generate netlist.
b. On the Summary tab, if available, select the files you want to generate. A gray checkmark indicates
a file that is automatically generated. All other files are optional.
Note: If file selection is supported for your IP core, after you generate the core, a generation report
(.html)appears in your project directory. This file contains information
about the generated files.
7. Click the Finish button, the parameter editor generates the top-level HDL code for your IP core, and a
simulation directory which includes files for simulation.
UG-01080
2015.01.19
MegaWizard Plug-In Manager Flow 2-3
Getting Started Overview Altera Corporation
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