Interfaces for stratix v native phy, Common interface ports for stratix v native phy, Interfaces for stratix v native phy -46 – Altera Transceiver PHY IP Core User Manual
Page 344
In addition you have the following options:
• You can toggle the
Data Pattern Select
bit switch between two data patterns.
• You can change the value of
Seed A
and
Seed B
.
Unlike the PRBS pattern generator, the pseudo-random pattern generator does not require a configurable
clock.
Square Wave Generator
To enable the square wave, write the following bits:
• Write 1'b1 to the
TX Test Enable
bit.
• Write 1'b1 to the
Square Wave Clock Enable
bit.
• Write 1'b1 to the
TX Test Select
bit.
• Write the
Square Wave Pattern
to 1, 4, 5, 6, 8 or 10 consecutive 1s or 0s.
The RX datapath does not include a verifier for the square wave and does drive a clock.
Interfaces for Stratix V Native PHY
This section describes the common, Standard and 10G PCS interfaces for the Stratix V Native PHY.
The Native PHY includes several interfaces that are common to all parameterizations. It also has separate
interfaces for the Standard and 10G PCS datapaths. If you use dynamic reconfiguration to change between
the Standard and 10G PCS datapaths, your top-level HDL file includes the port for both the Standard and
10G PCS datapaths. In addition, the Native PHY allows you to enable ports, even for disabled blocks to
facilitate dynamic reconfiguration.
The Native PHY uses the following prefixes for port names:
• Standard PCS ports—tx_std_, rx_std_
• 10G PCS ports—tx_10g_, rx_10g_
• PMA ports—tx_pma_, rx_pma_
The port descriptions use the following variables to represent parameters:
•
•
—The number of PLLs
•
Common Interface Ports for Stratix V Native PHY
This section describes the interface ports for the Stratix V native PHY.
Common interface consists of reset, clock signals, serial interface ports, control and status ports, parallel
data ports, PMA ports and reconfig interface ports. The following figure illustrates these ports.
12-46
Interfaces for Stratix V Native PHY
UG-01080
2015.01.19
Altera Corporation
Stratix V Transceiver Native PHY IP Core