Transceiver reconfiguration interface, Transceiver reconfiguration interface -9 – Altera Transceiver PHY IP Core User Manual
Page 526
Signal Name
Direction
Description
reconfig_mif_read
Output
When asserted, signals an Avalon-MM read
request.
reconfig_mif_readdata[15:0]
Input
The read data.
reconfig_mif_waitrequest
Input
When asserted, indicates that the MIF Avalon-MM
slave is not ready to respond to a read request.
cal_busy_in
Input
In Arria V and Cyclone V devices, acts as a status
port for DCD calibration to prevent simultaneous
DCD calibration for multiple channels on the same
side of the device. This signal is only available
when you select Create optional calibration status
ports.
If your design includes more than 1 Transceiver
Reconfiguration Controller on the same side of the
FPGA, you must daisy chain the
tx_cal_busy
output ports to the
cal_busy
_in input ports on the
same side of the FPGA. Arria V devices require
DCD calibration for channels with data rates equal
to or greater than 4.9152 Gbps.
Transceiver Reconfiguration Interface
This section describes the signals that comprise the dynamic reconfiguration interface. The Transceiver
Reconfiguration Controller communicates with the PHY IP cores using this interface. In the following
table,
Controller.
Table 16-6: Transceiver Reconfiguration Interface
Signal Name
Direction
Description
reconfig_to_xcvr[(<n>×70)-
1:0]
Output
Parallel reconfiguration bus from the Transceiver
Reconfiguration Controller to the PHY IP Core.
reconfig_from_xcvr[(<n>×46)
-1:0]
Input
Parallel reconfiguration bus from the PHY IP core to the
Transceiver Reconfiguration Controller.
reconfig_busy
Output
When asserted, indicates that a reconfiguration
operation is in progress and no further reconfiguration
operations should be performed. You can monitor this
signal to determine the status of the Transceiver
Reconfiguration Controller. Alternatively, you can
monitor the
busy
bit of the
control
and
status
registers of any reconfiguration feature to determine the
status of the Transceiver Reconfiguration Controller.
UG-01080
2015.01.19
Transceiver Reconfiguration Interface
16-9
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation