Altera Transceiver PHY IP Core - Manual (Page 433)

Parameter Range Description
RX word aligner mode
bit_slip
sync_sm
manual
Specifies one of the following 3 modes for the
word aligner:
• Bit_slip : You can use bit slip mode to
shift the word boundary. For every rising
edge of the
rx_bitslip signal
, the word
boundary is shifted by 1 bit. Each bit-slip
removes the earliest received bit from the
received data
• Sync_sm : In synchronous state machine
mode, a programmable state machine
controls word alignment. You can only use
this mode with 8B/10B encoding. The data
width at the word aligner can be 10 or 20
bits. When you select this word aligner
mode, the synchronous state machine has
hysteresis that is compatible with XAUI.
However, when you select cpri for the
Standard PCS Protocol Mode, this option
selects the deterministic latency word
aligner mode.
• Manual : This mode Enables word
alignment by asserting the
rx_std_wa_
patternalign
. This is an edge sensitive
signal.
RX word aligner pattern length
7, 8, 10
16, 20, 32
Specifies the length of the pattern the word
aligner uses for alignment.
RX word aligner pattern (hex) User-specified Specifies the word aligner pattern in hex.
Number of word alignment patterns to
achieve sync
1-256
Specifies the number of valid word alignment
patterns that must be received before the
word aligner achieves synchronization lock.
The default is 3.
Number of invalid words to lose sync
1-256
Specifies the number of invalid data codes or
disparity errors that must be received before
the word aligner loses synchronization. The
default is 3.
Number of valid data words to
decrement error count
1-256
Specifies the number of valid data codes that
must be received to decrement the error
counter. If the word aligner receives enough
valid data codes to decrement the error count
to 0, the word aligner returns to synchroniza‐
tion lock.
Run length detector word count
0-63
Specifies the maximum number of contiguous
0s or 1s in the data stream before the word
aligner reports a run length violation.
14-22 Standard PCS Parameters for the Native PHY
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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