Altera Transceiver PHY IP Core User Manual
Page 159
Table 6-14: Avalon-MM PHY Management Interface
Signal Name
Direction
Description
phy_mgmt_clk
Input
Avalon-MM clock input.
There is no frequency restriction for Stratix V
devices; however, if you plan to use the same clock
for the PHY management interface and transceiver
reconfiguration, you must restrict the frequency
range of
phy_mgmt_clk
to 100–150 MHz to meet
the specification for the transceiver reconfiguration
clock. For Arria II GX, Cyclone IV GX, HardCopy
IV, and Stratix IV GX the frequency range is 37.5–
50 MHz.
phy_mgmt_clk_reset
Input
Global reset signal that resets the entire XAUI PHY.
This signal is active high and level sensitive.
phy_mgmt_addr[8:0]
Input
9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input
32-bit input data.
phy_mgmt_readdata[31:0]
Output
32-bit output data.
phy_mgmt_write
Input
Write signal. Asserted high.
phy_mgmt_read
Input
Read signal. Asserted high.
phy_mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write
request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
For more information about the Avalon-MM interface, including timing diagrams, refer to the Avalon
Interface Specifications.
The following table specifies the registers that you can access using the Avalon-MM PHY management
interface using word addresses and a 32-bit embedded processor. A single address space provides access
to all registers.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 6-15: XAUI PHY IP Core Registers
Word Addr
Bits
R/W
Register Name
Description
PMA Common Control and Status Registers
0x021 [31:0]
RW
cal_blk_powerdown
Writing a 1 to channel <
n
> powers down the
calibration block for channel <
n
>. This
register is not available for Stratix V devices.
UG-01080
2015.01.19
XAUI PHY Register Interface and Register Descriptions
6-19
XAUI PHY IP Core
Altera Corporation