Altera Transceiver PHY IP Core - Manual (Page 357)

Figure 12-7: Stratix V Native PHY 10G PCS Interfaces
Clocks
Frame
Generator
TX FIFO
RX FIFO
Block
Synchronizer
Frame
Synchronizer
Bit-Slip
Gearbox
Feature
64B/66B
BER
10G PCS Interface Ports
CRC32
tx_10g_coreclkin[-1:0]
rx_10g_coreclkin[-1:0]
tx_10g_clkout[-1:0]
rx_10g_clkout[-1:0]
rx_10g_clk33out[-1:0]t
tx_10g_control[8-1:0]
tx_10g_data_valid[-1:0]
tx_10g_fifo_full[-1:0]
tx_10g_fifo_pfull[-1:0]
tx_10g_fifo_empty[-1:0]
tx_10g_fifo_pempt[-1:0]y
tx_10g_fifo_del[-1:0]
tx_10g_fifo_insert[-1:0]
rx_10g_control[10-1:0]
rx_10g_fifo_rd_en[-1:0]
rx_10g_data_valid[-1:0]
rx_10g_fifo_full[-1:0]
rx_10g_fifo_pfull[-1:0]
rx_10g_fifo_empty[-1:0]
rx_10g_fifo_pempty[-1:0]
rx_10g_fifo_align_clr[-1:0]
rx_10g_fifo_align_en[-1:0]
rx_10g_align_val[-1:0]
rx_10g_fifo_del[-1:0]
rx_10g_fifo_insert[-1:0]
rx_10g_crc32err[-1:0]
tx_10g_diag_status[2-1:0]
tx_10g_burst_en[-1:0]
tx_10g_frame[-1:0]
rx_10g_frame[-1:0]
rx_10g_frame_lock[-1:0]
rx_10g_pyld_ins[-1:0]
rx_10g_frame_mfrm_err[-1:0]
rx_10g_frame_sync_err[-1:0]
rx_10g_scram_err[-1:0]
rx_10g_frame_skip_ins[-1:0]
rx_10g_frame_skip_err[-1:0]
rx_10g_frame_diag_err[-1:0]
rx_10g_frame_diag_status[2-1:0]
rx_10g_blk_lock[-1:0]
rx_10g_blk_sh_err[-1:0]
rx_10g_bitslip[-1:0]
tx_10g_bitslip[7-1:0]
rx_10g_clr_errblk_count[-1:0]
rx_10g_highber[-1:0]
rx_10g_clr_highber_cnt[-1:0]
PRBS
rx_10g_prbs_done
rx_10g_prbs_err
rx_10g_prbs_err_clr
The following table describes the signals available for the 10G PCS datapath. When you enable both the
10G and Standard datapaths, both sets of signals are included in the top-level HDL file for the Native
PHY.
Table 12-44: 10G PCS Interface Signals
The signals in the following table are shown when the Phase Compensation FIFO is used in FIFO mode.
Name Direction Description
Clocks
tx_10g_coreclkin
[-1:0] Input
TX parallel clock input that drive the write side of the TX
FIFO.
rx_10g_coreclkin
[-1:0]
Input RX parallel clock input that drives the read side of the RX
FIFO. .
UG-01080
2015.01.19
10G PCS Interface 12-59
Stratix V Transceiver Native PHY IP Core Altera Corporation
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