Altera Transceiver PHY IP Core User Manual
Page 696
Date
Document
Version
Changes Made
May 2011
1.2
• Added simulation section.
• Revised Figure 1–1 on page 1–1 to show the Transceiver
Reconfiguration Controller as a separately instantiated IP core.
• Added statement saying that the transceiver PHY IP cores do
not support the NativeLink feature of the Quartus II software.
• Revised reset section.
Getting Started
May 2011
1.2
• No changes from previous release.
10GBASE-R PHY Transceiver
May 2011
1.2
• Corrected frequency of
pll_ref_clk
. Should be 644.53125
MHz, not 644.53725 MHz.
• Renamed
reconfig_fromgxb
and
reconfig_togxb reconfig_
from_xcvr
and
reconfig_to_xcvr
, respectively.
XAUI PHY Transceiver
May 2011
1.2
• Added support for DDR XAUI
• Added support for Arria II GZ and HardCopy IV
• Added example testbench
• Renamed reconfig_fromgxb and reconfig_togxb reconfig_from_
xcvr and reconfig_to_xcvr, respectively.
• Updated definitions of rx_digital_reset and tx_digital_reset for
the soft XAUI implementation in XAUI PHY IP Core Registers.
• Changed description of rx_syncstatus register and signals to
specify 2 bits per channel in hard XAUI and 1 bit per channel in
soft XAUI implementations.
• Corrected bit sequencing for 0x084, 0x085 and 0x088 in XAUI
PHY IP Core Registers, as follows:
•
patterndetect
= 0x084, bits [15:8]
•
syncstatus
= 0x084, bits [7:0]
•
errordetect
= 0x085, bits [15:8]
•
disperr
= 0x085, bits [7:0]
•
rmfifofull
= 0x088, bits [7:4]
•
rmfifoempty
= 0x088, bits [3:0]
Interlaken PHY Transceiver
21-36
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core