Xaui phy ip core, Xaui phy ip core -1 – Altera Transceiver PHY IP Core User Manual
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XAUI PHY IP Core
6
2015.01.19
UG-01080
The Altera XAUI PHY IP Core implements the IEEE 802.3 Clause 48 specification to extend the
operational distance of the XGMII interface and reduce the number of interface signals.
XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the
Ethernet standard PHY component to one meter. The XAUI IP Core accepts 72-bit data (single data rate–
SDR XGMII) from the application layer at either 156.25 Mbps or 312.5 Mbps. The serial interface runs at
either 4 × 3.125 Gbps or 4 × 6.25 Gbps (DDR XAUI option).
Figure 6-1: XAUI PHY IP Core
XAUI IP Core
4 x 3.125 Gbps serial
or
4 x 6.5 Gbps serial
Altera FPGA
Hard PMA
PCS
8B/10B
Word Aligner
Phase Comp
SDR XGMII
72 bits @ 156.25 Mbps
or
72 bits @ 312.5 Mbps
Avalon-MM
Control & Status
4
4
For Stratix IV GX and GT devices, you can choose a hard XAUI physical coding sublayer (PCS) and
physical media attachment (PMA), or a soft XAUI PCS and PMA in low latency mode. You can also
combine both hard and soft PCS configurations in the same device, using all channels in a transceiver
bank. The PCS is only available in soft logic for Stratix V devices.
For more detailed information about the XAUI transceiver channel datapath, clocking, and channel
placement, refer to the “XAUI” section in the Transceiver Configurations in Stratix V Devices chapter of
the Stratix V Device Handbook.
Related Information
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