Altera Transceiver PHY IP Core - Manual (Page 463)

TX Data Word Description
tx_parallel_data[10]
Specifies the current disparity as follows:
• 1'b0 = positive
• 1'b1 = negative
Signal Definitions with 8B/10B Disabled
tx_parallel_data[-1:0]
TX data bus. is the width specified in the
component GUI.
tx_parallel_data[10:]
Unused . is the width specified in the
component GUI.
Table 14-40: Location of Valid Data Words for tx_parallel_data for Various FPGA Fabric to PCS
Parameterizations
The following table shows the valid 11-bit data words with and without the byte deserializer for single- and
double-word FPGA fabric to PCS interface widths.
Configuration Bus Used Bits
Single word data bus, byte deserializer disabled [10:0] (word 0)
Single word data bus, byte serializer enabled [32:22], [10:0] (words 0 and 2)
Double word data bus, byte serializer disabled [21:0] (words 0 and 1)
Double word data bus, byte serializer enabled [43:0] (words 0-3)
Table 14-41: Signal Definitions for rx_parallel_data with and without 8B/10B Encoding
This table shows the signals within
rx_parallel_data
that correspond to data, control, and status signals.
RX Data Word Description
Signal Definitions with 8B/10B Enabled
rx_parallel_data[-1:0]
RX data bus; is the width you specify in the
component GUI, typically 8 bits
rx_parallel_data[10]
Synchronization status
rx_parallel_data[11]
Disparity error
rx_parallel_data[12]
Pattern detect
rx_parallel_data[14:13]
The following encodings are defined:
• 2’b00: Normal data
• 2’b01: Deletion
• 2’b10: Insertion (or Underflow with 9’h1FE or
9’h1F7)
• 2’b11: Overflow
rx_parallel_data[15]
Running disparity value
Signal Definitions with 8B/10B Disabled
rx_parallel_data[9:0]
RX data bus
14-52 Common Interface Ports for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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