Altera Transceiver PHY IP Core User Manual
Page 451
Parameter
Range
Description
Enable TX 64b/66b encoder
On/Off
When you turn this option On, the 10G PCS
includes the TX 64b/66b encoder.
Enable TX 64b/66b encoder
On/Off
When you turn this option On, the 10G PCS
includes the RX 64b/66b decoder.
Scrambler and Descrambler Parameters
TX scrambler randomizes data to create transitions to create DC-balance and facilitate CDR circuits based
on the x
58
+ x
39
+1 polynomial. The scrambler operates in the following two modes:
• Synchronous—The Interlaken protocol requires synchronous mode.
• Asynchronous (also called self-synchronized)—The 10GBASE-R protocol requires this mode as
specified in IEEE 802.3-2008 Clause-49.
The descrambler block descrambles received data to regenerate unscrambled data using the x58+x39+1
polynomial. The following table describes the scrambler and descrambler parameters.
Table 14-31: Scrambler and Descrambler Parameters
Parameter
Range
Description
Enable TX scrambler
On/Off
When you turn this option On, the TX
10G PCS datapath includes the
scrambler function. This option is
available for the Interlaken and
10GBASE-R protocols.
TX scrambler seed
User-specified 15-
bit value
You must provide a different seed for
each lane. This parameter is only
required for the Interlaken protocol.
Enable RX scrambler
On/Off
When you turn this option On, the RX
10G PCS datapath includes the
scrambler function. This option is
available for the Interlaken and
10GBASE-R protocols.
Enable rx_10g_descram_err port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_descram_err
port.
Interlaken Disparity Generator and Checker
The Disparity Generator monitors the data transmitted to ensure that the running disparity remains
within a ±96-bit bound. It adds the 67th bit to indicate whether or not the data is inverted. The Disparity
Checker monitors the status of the 67th bit of the incoming word to determine whether or not to invert
bits[63:0] of the received word. The following table describes Interlaken disparity generator and checker
parameters.
14-40
10G PCS Parameters for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation
Arria V GZ Transceiver Native PHY IP Core