Altera Transceiver PHY IP Core - Manual (Page 206)

Word Addr Bits R/W Register Name Description
0x044
[31:0] RW
reset_fine_control You can use the
reset_fine_control
register to create your own reset sequence.
The reset control module, illustrated in
Transceiver PHY Top-Level Modules,
performs a standard reset sequence at
power on and whenever the
phy_mgmt_
clk_reset
is asserted. Bits [31:4, 0] are
reserved.
[31:4] RW Reserved It is safe to write 0s to reserved bits.
[3] RW
reset_rx_digital
Writing a 1 causes the RX digital reset
signal to be asserted, resetting the RX digital
channels enabled in
reset_ch_bitmask
.
You must write a 0 to clear the reset
condition.
[2] RW
reset_rx_analog
Writing a 1 causes the internal RX digital
reset signal to be asserted, resetting the RX
analog logic of all channels enabled in
reset_ch_bitmask
. You must write a 0 to
clear the reset condition.
[1] RW
reset_tx_digital Writing a 1 causes the internal TX digital
reset signal to be asserted, resetting all
channels enabled in
reset_ch_bitmask
.
You must write a 0 to clear the reset
condition.
Refer to Timing Constraints for Reset
Signals when Using Bonded PCS Channels
for a SDC constraint you must include in
your design.
[0] RW
pll_powerdown
Writing a 1 causes the internal TX PLL to
powerdown. If you reset the transceiver,
you must assert
pll_powerdown
by writing
a 1 to this register and then writing a 0 after
1 ms.
PMA Control and Status Registers
0x061 [31:0] RW
phy_serial_loopback
Writing a 1 to channel <n> puts channel
<n> in serial loopback mode.
0x063 [31:0] R
pma_rx_signaldetect
When channel <n> =1, indicates that
receive circuit for channel <n> senses the
specified voltage exists at the RX input
buffer. This option is only operational for
the PCI Express PHY IP Core.
8-18 PHY for PCIe (PIPE) Register Interface and Register Descriptions
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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