Altera Transceiver PHY IP Core - Manual (Page 227)

Name Value Description
Byte ordering pad pattern 00000000 Specifies the pad pattern that is inserted to
align the SOP. Enter the following size pad
patterns:
Data Width 8B/10B
Encoded?
Pad Pattern
8, 16, 32 No
10,20,40 No 10 bits
8, 16, 3 No 9 bits
PLL Reconfiguration Parameters
Table 9-10: PLL Reconfigurations
Name Value Description
Allow PLL Reconfiguration On/Off You must enable this option if you plan to
reconfigure the PLLs in your design. This
option is also required to simulate PLL
reconfiguration.
Number of TX PLLs 1-4
Specifies the number of TX PLLs that can be
used to dynamically reconfigure channels to
run at multiple data rates. If your design does
not require transceiver TX PLL dynamic
reconfiguration, set this value to 1. The
number of actual physical PLLs that are
implemented depends on the selected clock
network. Each channel can dynamically select
between n PLLs, where n is the number of
PLLs specified for this parameter.
You must disable the embedded reset
controller and design your own controlled
reset controller or the use the highly configu‐
rable reset core described in "Transceiver
Reconfiguration Controller IP Core" if you
intend to use more than 1 TX PLL for a
Custom PHY IP instance.
Note: For more details, refer to the
Transceiver Clocking chapter in the
device handbook for the device
family you are using.
9-14 PLL Reconfiguration Parameters
UG-01080
2015.01.19
Altera Corporation Custom PHY IP Core
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