Altera Transceiver PHY IP Core - Manual (Page 467)

Name Dir Synchro‐
nous to tx_
std_
coreclkin/
rx_std_
coreclkin
Description
rx_std_polinv[-1:0] Input No Polarity inversion for the 8B/10B decoder,
When set, the RX channels invert the
polarity of the received data. You can use
this signal to correct the polarity of
differential pairs if the transmission
circuitry or board layout mistakenly
swapped the positive and negative signals.
The polarity inversion function operates
on the word aligner input.
tx_std_polinv[-1:0] Input No Polarity inversion, part of 8B10B encoder,
When set, the TX interface inverts the
polarity of the TX data.
Rate Match FIFO
rx_std_rmfifo_empty[-
1:0]
Output No Rate match FIFO empty flag. When
asserted, the rate match FIFO is empty.
This port is only used for XAUI, GigE, and
Serial RapidIO in double width mode. In
double width mode, the FPGA data width
is twice the PCS data width to allow the
fabric to run at half the PCS frequency
rx_std_rmfifo_full[-
1:0]
Output No Rate match FIFO full flag. When asserted
the rate match FIFO is full. You must
synchronize this signal. This port is only
used for XAUI, GigE, and Serial RapidIO
in double width mode.
Word Aligner
rx_std_bitrev_ena[-
1:0]
Input No When asserted, enables bit reversal on the
RX interface. Bit order may be reversed if
external transmission circuitry transmits
the most significant bit first. When
enabled, the receive circuitry receives all
words in the reverse order. The bit reversal
circuitry operates on the output of the
word aligner.
14-56 Standard PCS Interface Ports
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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