Altera Transceiver PHY IP Core User Manual
Page 235
Table 9-14: Avalon-ST RX Interface Signals
These signals are driven from the PCS to the MAC. This is an Avalon source interface.
Signal Name
Direction
Description
rx_parallel_data[
Output
This is RX parallel data driven from the Custom
PHY IP Core. The ready latency on this interface
is 0, so that the MAC must be able to accept data
as soon as the PHY comes out of reset. Data
driven from this interface is always valid.
The bits of each 16-bit word have the following
definitions when you enable 8B/10B decoding:
•
rx_parallel_data[7:0]
: RX data bus
•
rx_parallel_data[8]
: RX data control
character
•
rx_parallel_data[9]
: Code violation
•
rx_parallel_data[10]
: Word alignment
status
•
rx_parallel_data[11]
: Disparity error
•
rx_parallel_data[12]
: Pattern detect
•
rx_parallel_data[14:13]
• 2'b00: Normal data
• 2'b01: Deletion
• 2'b10: Insertion (or Underflow with 9'h1FE
or 9'h1F7
• 2'b11: Overflow
•
rx_parallel_data[14:13]
: Running disparity
value
If 8B/10B decoding is disabled, the width of this
interface is width you specified for FPGA fabric
transceiver interface width. If 8B/10B encoding is
disabled, when you have enabled dynamic reconfi‐
guration, the following mapping applies to each
word:
•
rx_parallel_data[9:0]
: RX data bus
•
rx_parallel_data[10]
: Sync status
•
rx_parallel_data[11]
: Disparity error
•
rx_parallel_data[12]
: Pattern detect
•
rx_parallel_data[14:13]
• 2'b00: Normal data
• 2'b01: Deletion
• 2'b10: Insertion (or Underflow with 9'h1FE
or 9'h1F7
• 2'b11: Overflow
•
rx_parallel_data[15]
: Running disparity
value
Refer to
for the location of valid data
for a single- and double-word data buses, with and
without the byte serializer.
9-22
Data Interfaces
UG-01080
2015.01.19
Altera Corporation
Custom PHY IP Core