Altera Transceiver PHY IP Core - Manual (Page 359)

Name Direction Description
tx_10g_control
[9-1:0] (continued)
• [2]: Inversion signal, must always be set to 1'b0.
• [1]: Sync Header, 1 indicates a control word
• [0]: Sync Header, 1 indicates a data word
10G BaseR mode:
• [8]: Active-high synchronous error insertion control
signal
• [7]: MII control signal for
tx_data[63:56]
• [6]: MII control signal for
tx_data[55:48]
• [5]: MII control signal for
tx_data[47:40]
• [4]: MII control signal for
tx_data[39:32]
• [3]: MII control signal for
tx_data[31:24]
• [2]: MII control signal for
tx_data[23:16]
• [1]: MII control signal for
tx_data[15:8]
• [0]: MII control signal for
tx_data[7:0]
Basic mode: 67-bit word width:
• [8:3]: Not used
• [2]: Inversion Bit - must always be set to 1'b0.
• [1]: Sync Header, 1 indicates a control word)
• [0]: Sync Header, 1 indicates a data word)
Basic mode: 66-bit word width:
• [8:2]: Not used
• [1]: Sync Header, 1 indicates a control word)
• [0]: Sync Header, 1 indicates 1 data word)
Basic mode: 64-bit, 50-bit, 40-bit, 32-bit word widths:
[8:0]: Not used
tx_10g_data_valid
[-1:0]
Input
When asserted, indicates if
tx_data
is valid. Synchronous
to
tx_10g_coreclk_in
. Use of this signal depends upon
the protocol you are implementing, as follows:
• 10G BASE-R: Tie to 1'b1
• Interlaken: Acts as control for FIFO write enable. You
should tie this signal to
tx_10g_fifo_pempty
.
• Basic with phase compensation FIFO: Tie to 1'b1 as
long as
tx_coreclkin = data_rate/pld_pcs
interface width
. Otherwise, tie this signal to
tx_
10g_fifo_pempty.
• Basic with phase compensation FIFO in register mode.
This mode only allows a 1:1 gear box ratio such as
32:32 and 64:64; consequently, you can tie
tx_10g_
data_valid
to 1’b1.
tx_10g_fifo_full
[-1:0]
Output When asserted, indicates that the TX FIFO is full.
Synchronous to
tx_10g_coreclkin
.
UG-01080
2015.01.19
10G PCS Interface 12-61
Stratix V Transceiver Native PHY IP Core Altera Corporation
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