Altera Transceiver PHY IP Core - Manual (Page 362)

Name Direction Description
rx_10g_control
[10-1:0] (continued)
Basic mode: 67-bit mode with Block Sync:
• [9]: Active-high synchronous status signal that
indicates when Block Lock is achieved.
• [8]: Active-high synchronous status signal that
indicates a sync header error
• [7:3]: Not used [2]: Used
• [1]: Synchronization header, a 1 indicates control
word
• [0]: Synchronization header, a 1 indicates data word
Basic mode: 66-bit mode with Block Sync:
[9]: Active-high synchronous status signal that indicates
when Block Lock is achieved.
[8]: Active-high synchronous status signal that indicates a
sync header error.
[7:2]: Not used
• [1]: Synchronization header, a 1 indicates control
word
• [0]: Synchronization header, a 1 indicates data word
Basic mode: 67-bit mode without Block Sync:
[9:3]: Not used
66-bit mode without Block Sync:
[9:2]: Not used
• [1]: Synchronization header, a 1 indicates control
word
• [0]: Synchronization header, a 1 indicates data word
Basic mode: 64-bit, 50-bit, 40-bit and 32-bit modes:
[9:0]: Not used
rx_10g_fifo_rd_en
[-1:0]
Input Active high read enable signal for RX FIFO. Asserting
this signal reads 1 word from the RX FIFO.
rx_10g_data_valid
[-1:0]
Output Active valid data signal with the following use:
• 10GBASE-R: Always high
• Interlaken: Toggles indicating when
rx_data
is valid.
• Basic - Phase compensation: Toggles indicating when
rx_data
is valid.
• Basic - Register: Toggles indicating when
rx_data
is
valid.
12-64 10G PCS Interface
UG-01080
2015.01.19
Altera Corporation Stratix V Transceiver Native PHY IP Core
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