Altera Transceiver PHY IP Core User Manual
Page 684
Date
Document
Version
Changes Made
November 2012
1.8
• Added Gen3 support.
• Added Arria V GZ support.
• Added ×2 support.
• Added discussion of link equalization for Gen3.
• Added timing diagram showing rate change to Gen3.
• Revised presentation of signals.
• Corrected the definition of
rx_eidleinfersel[3
.
• Moved Analog Options to a separate chapter.
• Updated section on Logical Lane Assignment Restrictions.
• Removed the following statement from the definition of
pll_
powerdown
. Asserting
pll_powerdown
no longer powers down
tx_analogreset
.
tx_analogreset
is a separate signal.
Custom PHY IP Core
November 2012
1.8
• Added Cyclone V support.
• Moved Analog Options to a separate chapter.
• Added constraint for tx_digitalreset when TX PCS uses bonded
clocks.
• Corrected description of manual word alignment mode.
Low Latency PHY IP Core
November 2012
1.8
• Added Cyclone V support.
• Moved Analog Options to a separate chapter.
• Added constraint for
tx_digitalreset
when TX PCS uses
bonded clocks.
• Added RX bitslip option for the word aligner when the 10G PCS
is selected.
• Added description of
reset_fine_control
register at 0x044.
This register is available when not using the embedded reset
controller.
Deterministic Latency PHY IP Core
November 2012
1.8
• Added Cyclone V support.
• Moved Analog Options to a separate chapter.
Stratix V Transceiver Native PHY
November 2012
1.8
• Added support for Standard and 10G datapaths.
• Added QPI interface.
• Moved Analog Options to a separate chapter.
• Added constraint for
tx_digitalreset
when TX PCS uses
bonded clocks.
21-24
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core