Altera Transceiver PHY IP Core - Manual (Page 275)

PCS Datapath Width RX Phase
Comp FIFO
Byte
Ordering
Deserial‐
izer
8B/10B Word
Aligner (10)(9)
Total RX Parallel
Clock Cycles (9)(10)
16 bits 1.0 1.0 1.0 1.0 5.0 9.0
Byte Serializer/Deserializer Turned On
16 bits 1.0 1.0 0.5 or 1.0 0.5 2.0 5.0 or 5.5
32 bits 1.0 1.0 0.5 or 1.0 0.5 2.5 5.5 or 6.0
Table 11-4: PMA Datapath Total Latency
The latency numbers in this table are actual hardware delays .
Device
RX PMA Latency in UI TX PMA Latency in UI
PCS to PMA
Width 10 bits
PCS to PMA
Width 20 bits
PCS to PMA
Width 10 bits
PCS to PMA Width 20 bits
Cyclone V 26 31 42 62
Arria V 34 49 52 82
Stratix V 26 31 53 83
Deterministic Latency PHY Device Family Support
This section describes Deterministic Latency PHY IP core device support.
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 11-5: Device Family Support
Device Family Support
Arria V devices Final
Arria V GZ devices Final
Cyclone V devices Final
Stratix V devices Final
Other device families No support
UG-01080
2015.01.19
Deterministic Latency PHY Device Family Support 11-7
Deterministic Latency PHY IP Core Altera Corporation
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