Altera Transceiver PHY IP Core - Manual (Page 483)

Example 14-5: Overriding Logical Channel 0 Channel Assignment Restrictions in Arria V GZ
Device for ×6 or ×N Bonding
If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign
the starting channel number. Logical channel 0 should be assigned to either physical transceiver
channel 1 or channel 4 of a transceiver bank. However, if you have already created a PCB with a
different lane assignment for logical lane 0, you can use the workaound shown in the following
example to remove this restriction. The following example redefines the pma_bonding_master
parameter using the Quartus II Assignment Editor. In this example, the pma_bonding_master
was originally assigned to physical channel 1. (The original assignment could also have been to
physical channel 4.) The to parameter reassigns the pma_bonding_master to the Deterministic
Latency PHY instance name. You must substitute the instance name from your design for the
instance name shown in quotation marks
set_parameter -name pma_bonding_master "\"1\"" -to ""
Simulation Support
The Quartus II release provides simulation and compilation support for the Arria V GZ Native PHY IP
Core. Refer to Running a Simulation Testbench for a description of the directories and files that the
Quartus II software creates automatically when you generate your Arria V GZ Transceiver Native PHY IP
Core.
14-72 Simulation Support
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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