Altera Transceiver PHY IP Core - Manual (Page 562)

write_32 0x3A 0x5
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Incrementing Streamer offset register offset address
write_32 0x3B 0x1
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Setting data register with the second data record
write_32 0x3C 16'b0010001110110000
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Writing second data to the Streamer
write_32 0x3A 0x5
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Incrementing Streamer offset register offset address
write_32 0x3B 0x2
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Setting data register with the third data record
write_32 0x3C 16'b1000000111010100
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Writing third data record to the Streamer
write_32 0x3A 0x5
#Read the busy bit to determine when the operation completes
read_32 0x3a
#Read the busy bit to determine when the operation completes
read_32 0x3a
Streamer-Based Reconfiguration
Follow these steps to reconfigure a transceiver setting by streaming the contents of a MIF file through the
Streamer Module.
1. Write the logical channel number to the Streamer
logical channel
register.
2. Write MIF mode, 2’b00, to the Streamer
control and status
register mode bits.
3. Write the MIF base address, 0x0, to the Streamer
offset
register.
4. Write the base address of the MIF file to the Streamer
data
register.
5. Write the Streamer
control and status
register
write
bit to 1'b1 to initiate a write of all the data set
in the previous steps.
6. Write to the Streamer
offset
register with the value to start a MIF stream, 0x1.
7. Write the Streamer internal
data
register with the value 0x3 to setup the streaming of the MIF.
8. Write to the Streamer
control and status
register to 1'b1, to initiate the streaming operation.
9. Read the
control and status
register
busy
bit. When the
busy
bit is deasserted, the MIF streaming
operation has completed.
The following example illustrates the reconfiguration of logical channel 0 using a MIF with a base address
of 0x100.
Example 16-11: Reconfiguration of Logical Channel 0 Using a MIF
#Setting logical channel 0
write_32 0x38 0x0
#Setting Streamer mode to 0
write_32 0x3A 0x0
#Setting Streamer offset register to the MIF base address (0x0)
UG-01080
2015.01.19
Streamer-Based Reconfiguration 16-45
Transceiver Reconfiguration Controller IP Core Overview Altera Corporation
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