Altera Transceiver PHY IP Core - Manual (Page 291)

Figure 11-4: Deterministic Latency PHY IP Core
System
Interconnect
Fabric
System
Interconnect
Fabric
Deterministic PHY PCS and PMA
Deterministic PHY IP Core
Resets
Status
Control S
Avalon-MM
Control
S Avalon-MM
Status
Reset
Controller
PLL
Reset
Clocks Clocks
to
Transceiver
Reconfiguration
Controller
to
Embedded
Controller
Tx Data Tx Parallel Data
Rx Data Rx Parallel Data
M
Avalon-MM
PHY
Mgmt
S
Rx Serial Data & Status
Reconfig to and from Transceiver
Tx Serial Data
Table 11-17: Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk
Input Avalon-MM clock input. There is no frequency
restriction for Stratix V devices; however, if you plan
to use the same clock for the PHY management
interface and transceiver reconfiguration, you must
restrict the frequency range of
phy_mgmt_clk
to 100-
150 MHz to meet the specification for the transceiver
reconfiguration clock.
phy_mgmt_clk_reset
Input Global reset signal. This signal is active high and level
sensitive.
phy_mgmt_address[8:0]
Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input Input data.
phy_mgmt_readdata[31:0]
Output Output data.
phy_mgmt_write
Input Write signal.
phy_mgmt_read
Input Read signal.
UG-01080
2015.01.19
Register Interface and Descriptions for Deterministic Latency PHY 11-23
Deterministic Latency PHY IP Core Altera Corporation
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