Altera Transceiver PHY IP Core - Manual (Page 459)

Name Direction Description
Resets
pll_powerdown
[ -1:0]
Input When asserted, resets the TX PLL. Active high,
edge sensitive reset signal. By default, the Arria
V GZ Native Transceiver PHY IP Core creates
a separate
pll_powerdown
signal for each
logical PLL. However, the Fitter may merge the
PLLs if they are in the same transceiver bank.
PLLs can only be merged if their
pll_
powerdown
signals are driven from the same
source. If the PLLs are in separate transceiver
banks, you can choose to drive the
pll_
powerdown
signals separately.
tx_analogreset
[ -1:0]
Input When asserted, resets for TX PMA, TX clock
generation block, and serializer. Active high,
edge sensitive reset signal.
tx_digitalreset
[ -1:0]
Input When asserted, resets the digital components of
the TX datapath. Active high, edge sensitive
reset signal.If your design includes bonded TX
PCS channels, refer to Timing Constraints for
Reset Signals when Using Bonded PCS Channels
for a SDC constraint you must include in your
design.
rx_analogreset
[ -1:0]
Input When asserted, resets the RX CDR, deserializer,
Active high, edge sensitive reset signal.
rx_digitalreset
[ -1:0]
Input When asserted, resets the digital components of
the RX datapath. Active high, edge sensitive
reset signal.
Parallel Data Ports
tx_pma_parallel_data
[ 80-1:0]
Input TX parallel data for the PMA Direct datapath.
Driven directly from the FPGA fabric to the
PMA. Not used when you enable either the
Standard or 10G PCS datapath.
rx_pma_parallel_data
[ 80-1:0]
Output RX PMA parallel data driven from the PMA to
the FPGA fabric. Not used when you enable
either the Standard or 10G PCS datapath.
14-48 Common Interface Ports for Arria V GZ Native PHY
UG-01080
2015.01.19
Altera Corporation Arria V GZ Transceiver Native PHY IP Core
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