Altera Transceiver PHY IP Core - Manual (Page 454)

Table 14-35: PRBS Parameters
Parameter Range Description
Enable rx_10g_prbs ports On/Off When you turn this option On, the PCS
includes the
rx_10g_prbs_done
,
rx_10g_
prbs_err
and
rx_10g_prbs_err_clr
signals
to provide status on PRBS operation.
Related Information
Transceiver Archictecture in Arria V GZ Devices
10G PCS Pattern Generators
The 10G PCS supports the PRBS, pseudo-random pattern, and square wave pattern generators. You
enable the pattern generator or verifiers in the 10G PCS, by writing a 1 to the
TX Test Enable
and
RX
Test Enable
bits. The following table lists the offsets and registers of the pattern generators and verifiers
in the 10G PCS.
Note: The 10G PRBS generator inverts its pattern before transmission. The 10G PRBS verifier inverts the
received pattern before verification. You may need to invert the patterns if you connect to third-
party PRBS pattern generators and checkers.
Note: Note: All undefined register bits are reserved.
Table 14-36: Pattern Generator Registers
Offset Bits R/W Name Description
0x12D [15:0]
R/W
Seed A for PRP
Bits [15:0] of seed A for the pseudo-
random pattern.
0x12E [15:0] Bits [31:16] of seed A for the pseudo-
random pattern.
0x12F [15:0] Bits [47:21] of seed A for the pseudo-
random pattern.
0x130 [9:0] Bits [57:48] of seed A for the pseudo-
random pattern.
0x131 [15:0]
R/W
Seed B for PRP
Bits [15:0] of seed B for the pseudo-
random pattern.
0x132 [15:0] Bits [31:16] of seed B for the pseudo-
random pattern.
0x133 [15:0] Bits [47:32] of seed B for the pseudo-
random pattern.
0x134 [9:0] Bits [57:48] of seed B for the pseudo-
random pattern.
UG-01080
2015.01.19
10G PCS Pattern Generators 14-43
Arria V GZ Transceiver Native PHY IP Core Altera Corporation
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