Altera Transceiver PHY IP Core User Manual
Page 504
Parameter
Range
Description
Enable TX polarity inversion
On/Off
When you turn this option On, the
tx_
std_polinv
port controls polarity
inversion of TX parallel data before
transmitting the parallel data to the
PMA.
Enable RX polarity inversion
On/Off
When you turn this option On,
asserting
rx_std_polinv
controls
polarity inversion of RX parallel data
after PMA transmission.
Enable rx_std_bitrev_ena port
On/Off
When you turn this option On,
asserting
rx_std_bitrev_ena
control
port causes the RX data order to be
reversed from the normal order, LSB to
MSB, to the opposite, MSB to LSB.
This signal is an asynchronous input.
Enable rx_std_byterev_ena port
On/Off
When you turn this option On,
asserting
rx_std_byterev_ena
input
control port swaps the order of the
individual 8 or 10bit words received
from the PMA.
Enable tx_std_polinv port
On/Off
When you turn this option On, the
tx_
std_polinv
input is enabled. You can
use this control port to swap the
positive and negative signals of a serial
differential link if they were
erroneously swapped during board
layout.
Enable rx_std_polinv port
On/Off
When you turn this option On, the
rx_
std_polinv
input is enabled. You can
use this control port to swap the
positive and negative signals of a serial
differential link if they were
erroneously swapped during board
layout.
Enable tx_std_elecidle port
On/Off
When you turn this option On, the
tx_
std_elecidle
input port is enabled.
When this signal is asserted, it forces
the transmitter to electrical idle.
UG-01080
2015.01.19
Bit Reversal and Polarity Inversion
15-21
Cyclone V Transceiver Native PHY IP Core Overview
Altera Corporation