Simulation files and example testbench, Simulation files and example testbench -21 – Altera Transceiver PHY IP Core User Manual

Page 268

Related Information

SDC Timing Constraints of Stratix V Native PHY

on page 12-74

This section describes SDC examples and approaches to identify false timing paths.

Simulation Files and Example Testbench

Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II

software creates automatically when you generate your Low Latency PHY IP Core.
Refer to the

for an example testbench that you can use as a starting point in creating your own

verification environment.

UG-01080

2015.01.19

Simulation Files and Example Testbench

10-21

Low Latency PHY IP Core

Altera Corporation

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