Altera Transceiver PHY IP Core User Manual
Page 292
Signal Name
Direction
Description
phy_mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write
request. When asserted, control signals to the Avalon-
MM slave interface must remain constant.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
This table specifies the registers that you can access over the PHY management interface using word
addresses and a 32-bit embedded processor. A single address space provides access to all registers.
Table 11-18: Deterministic Latency PHY IP Core Registers
Word Addr
Bits
R/W
Register Name
Description
PMA Common Control and Status Registers
0x021
[31:0]
RW
cal_blk_powerdown
Writing a 1 to channel < n > powers
down the calibration block for
channel < n > .
0x022
[31:0]
R
pma_tx_pll_is_locked
Bit[P] indicates that the TX CMU
PLL (P) is locked to the input
reference clock. There is typically one
pma_tx_pll_is_locked bit per system.
Reset Control Registers–Automatic Reset Controller
0x041
[31:0]
RW
reset_ch_bitmask
Reset controller channel bitmask for
digital resets. The default value is all
1s. Channel < n > can be reset when
bit< n > = 1.
0x42
[1:0]
W
reset_control (write)
Writing a 1 to bit 0 initiates a TX
digital reset using the reset controller
module. The reset affects channels
enabled in the
reset_ch_bitmask
.
Writing a 1 to bit 1 initiates a RX
digital reset of channels enabled in
the
reset_ch_bitmask
.
R
reset_status (read)
Reading bit 0 returns the status of the
reset controller TX ready bit.
Reading bit 1 returns the status of the
reset controller RX ready bit.
Reset Controls –Manual Mode
11-24
Register Interface and Descriptions for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation
Deterministic Latency PHY IP Core