Altera Transceiver PHY IP Core - Manual (Page 273)

Example 11-1: For RE
RX _latency_ RE =
+ (
+ <
TX_latency_RE =
+ Tx bitslip latency > +
rx_std_bitslipboundaryselect > delay )
Note:
In single width (PMA =10) mode, add one UI delay per value of
rx_std_bitslipboundaryselect
. For
constant round-trip delay (RX+TX), set
tx_std_bitslipboundaryselect
<= (5'd9 -
rx_std_bitslip-
boundaryselect
).
In double width (PMA =20) mode, add one UI delay per value of (5'd9 -
rx_std_bitslipboundaryse-
lect
). For constant round-trip delay (RX+TX), set
tx_std_bitslipboundaryselect
<=
rx_std_bitslipboundaryselect
.
Example 11-2: For REC
For REC
=
+ +
TX_latency_REC =
+
RX_latency_REC
Example 11-3: For Round Trip Delay
Launch_time (from TX pins) = +
=
+ (tx bits lip=0 )
=
PD
G P L L to CM U P L L - t
feedback
>
+ (( × )
+ t
TX_tc lock_output
)
= in RE > -
= ( × )
– (( × )
+
PDI O >R X_ deser
>
+ × rx _clkout_period> )
Arrival_time (at RX pins)
Total Delay = -
UG-01080
2015.01.19
Deterministic Latency PHY Delay Estimation Logic 11-5
Deterministic Latency PHY IP Core Altera Corporation
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