Altera Transceiver PHY IP Core - Manual (Page 169)

The Interlaken PCS supports the following framing functions on a per lane basis:
• Gearbox
• Block synchronization
• Metaframe generation and synchronizatio
• 64b/67b encoding and decoding
• Scrambling and descrambling
• Lane-based CRC32
• Disparity DC balancing
For more detailed information about the Interlaken transceiver channel datapath, clocking, and channel
placement in Stratix V devices, refer to the “Interlaken” section in the Transceiver Configurations in
Stratix V Devices chapter of the Stratix V Device Handbook.
For more detailed information about the Interlaken transceiver channel datapath, clocking, and channel
placement in Arria V GZ devices, refer to the “Interlaken” section in the Transceiver Configurations in
Arria V Devices chapter of the Arria V Device Handbook.
Refer to PHY IP Design Flow with Interlaken for Stratix V Devices for a reference design that implements
the Interlaken protocol in a Stratix V device.
Related Information
• Interlaken Protocol Specification, Rev 1.2
• Avalon Interface Specifications
• Transceiver Configurations in Stratix V Devices
• Transceiver Configurations in Arria V Devices
• PHY IP Design Flow with Interlaken for Stratix V Devices
Interlaken PHY Device Family Support
This section describes the Interlaken PHY device family support.
IP cores provide either final or preliminary support for target Altera device families. These terms have the
following definitions:
• Final support—Verified with final timing models for this device.
• Preliminary support—Verified with preliminary timing models for this device.
Table 7-1: Device Family Support
Device Family Support
Arria V GZ devices–Hard PCS + PMA Final
Stratix V devices–Hard PCS + PMA Final
Other device families Not supported
7-2 Interlaken PHY Device Family Support
UG-01080
2015.01.19
Altera Corporation Interlaken PHY IP Core
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