Altera Transceiver PHY IP Core - Manual (Page 32)

Table 3-6: 10GBASE-R PHY Performance and Resource Utilization—Arria V GT Device
Channels ALMs Primary Logic
Registers
Secondary Logic
Registers
Memory 10K
1 2800 3000 300 7
Related Information
Fitter Resources Reports
10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and
Stratix V Devices
Because the 10GBASE-R PHY is implemented in hard logic in Arria V GZ and Stratix V devices, it uses
less than 1% of the available ALMs, memory, primary and secondary logic registers.
The following table lists the total latency for an Ethernet packet with a 9600 byte payload and an inter-
packet gap of 12 characters. The latency includes the number of cycles to transmit the payload from the
TX XGMII interface, through the TX PCS and PMA, looping back through the RX PMA and PCS to the
RX XGMII interface. (Stratix V Clock Generation and Distribution illustrates this datapath.)
Table 3-7: Latency
PPM Difference Cycles
0 PPM 35
-200 PPM 35
+200 PPM 42
Note: If latency is critical, Altera recommends designing your own soft 10GBASE-R PCS and connecting
to the Low Latency PHY IP Core.
Parameterizing the 10GBASE-R PHY
The 10GBASE-R PHY IP Core is available for the Arria V, Arria V GZ, Stratix IV, or Stratix V device
families. Complete the following steps to configure the 10GBASE-R PHY IP Core:
1. Under Tools > IP Catalog, select the device family of your choice.
2. Under Tools > IP Catalog > Interface Protocols > Ethernet > select 10GBASE-R PHY.
3. Use the tabs on the MegaWizard Plug-In Manager to select the options required for the protocol.
4. Refer to the following topics to learn more about the parameters:
a. General Option Parameters on page 3-9
b. Analog Parameters for Stratix IV Devices on page 3-12
5. Click Finish to generate your parameterized 10GBASE-R PHY IP Core.
3-8 10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V
Devices
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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