Altera Transceiver PHY IP Core User Manual
Page 186
Word Addr
Bits
R/W
Register Name
Description
0x065
[31:0]
RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to
lock to the reference clock. Bit <
n
>
corresponds to channel <
n
>. By default,
the Interlaken PHY IP configures the
CDR PLL in Auto lock Mode. This bit is
part of the CDR PLL Manual Lock Mode
which is not the recommended usage.
0x066
[31:0]
RO
pma_rx_is_
lockedtodata
When asserted, indicates that the RX
CDR PLL is locked to the RX data, and
that the RX CDR has changed from LTR
to LTD mode. Bit <
n
> corresponds to
channel <
n
>.
00x067
[31:0]
RO
pma_rx_is_
lockedtoref
When asserted, indicates that the RX
CDR PLL is locked to the reference
clock. Bit <
n
> corresponds to channel
<
n
>.
0x080
[31:0]
WO
indirect_addr
Provides for indirect addressing of all
PCS control and status registers. Use this
register to specify the logical channel
address of the PCS channel you want to
access.
Device Registers
[27]
RO
rx_crc32_err
Asserted by the CRC32 checker to
indicate a CRC error in the
corresponding RX lane.
From block: CRC32 checker.
0x081
[25]
RO
rx_sync_lock
Asserted by the frame synchronizer to
indicate that 4 frame synchronization
words have been received so that the RX
lane is synchronized.
From block: Frame synchronizer.
[24]
RO
rx_word_lock
Asserted when the first alignment
pattern is found. The RX FIFO generates
this synchronous signal.
From block: The RX FIFO generates this
synchronous signal.
Related Information
•
Introduction Overview
•
UG-01080
2015.01.19
Interlaken PHY Register Interface and Register Descriptions
7-19
Interlaken PHY IP Core
Altera Corporation