Altera Transceiver PHY IP Core - Manual (Page 383)

RX PMA Parameters
Note: For more information about the CDR circuitry, refer to the Receiver PMA Datapath section in the
Transceiver Architecture in Arria V Devices .
Table 13-6: RX PMA Parameters
Parameter Range Description
Enable CDR dynamic
reconfiguration
On/Off When you turn this option On, you can dynamically
change the data rate of the CDR circuit.
Number of CDR
reference clocks
1–5 Specifies the number of reference clocks for the CDRs.
Selected CDR reference
clock
0–4 Specifies the index of the selected CDR reference clock.
Selected CDR reference
clock frequency
Device Dependent Specifies the frequency of the clock input to the CDR.
PPM detector threshold +/- 1000 PPM Specifies the maximum PPM difference the CDR can
tolerate between the input reference clock and the
recovered clock.
Enable rx_pma_clkout
port
On/Off When you turn this option On, the RX parallel clock
which is recovered from the serial received data is an
output of the PMA.
Enable rx_is_lockedto‐
data port
On/Off When you turn this option On, the
rx_is_lockedto-
data
port is an output of the PMA.
Enable rx_is_lockedtoref
port
On/Off When you turn this option On, the
rx_is_lockedtoref
port is an output of the PMA.
Enable rx_set_lockedto‐
data and rx_set_
locktoref ports
On/Off When you turn this option On, the
rx_set_lockedt-
data
and
rx_set_lockedtoref
ports are outputs of the
PMA.
Enable rx_pma_bitslip_
port
On/Off When you turn this option On, the
rx_pma_bitslip
is
an input to the core. The deserializer slips one clock edge
each time this signal is asserted. You can use this feature
to minimize uncertainty in the serialization process as
required by protocols that require a datapath with
deterministic latency such as CPRI.
Enable rx_seriallpbken
port
On/Off When you turn this option On, the
rx_seriallpbken
is
an input to the core. When your drive a 1 on this input
port, the PMA operates in serial loopback mode with TX
data looped back to the RX channel.
13-8 RX PMA Parameters
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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