Altera Transceiver PHY IP Core User Manual
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write_32 0x3B 0x0
#Setting data register with the MIF base address
write_32 0x3C 0x100
#Writing all data to the Streamer
write_32 0x3A 0x1
#Setting Streamer Module offset for Start MIF stream
write_32 0x3B 0x1
#Setting data register with 0x3 to setup for streaming
write_32 0x3C 0x3
#Writing all data to the Streamer to start streaming the MIF
write_32 0x3A 0x1
#Read the busy bit to determine when the write has completed
read_32 0x3A
Pattern Generators for the Stratix V and Arria V GZ Native PHYs
Both the Standard and 10G PCS contain dedicated pattern generators that you can use for verification or
diagnostics. The pattern generator blocks support the following patterns:
• Pseudo-random binary sequence (PRBS)
• Pseudo-random pattern
• Square wave
You enable and disable the pattern generator using the Streamer module.
Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration
Complete the following reads and writes to the Streamer module to enable the PRBS verifier in the
Standard PCS. For example, using a 16-bit PCS/PMA width and a PRBS-23 pattern the corresponding
word aligner size is 3’b110 should be 3’b101 and word aligner pattern is 0x00007FFFFF.
1. Read the Streamer Module
control and status
register
busy
bit (7’h3A, bit[8]) until it is clear.
2. Write the Streamer Module logical channel number to the Streamer
logical channel number
register at address 0x38.
3. Set the Streamer Module
control and status
register
Mode
bits (7’h3A, bits[3:2]) to 1.
4. Determine the PRBS pattern from the table above and note the corresponding word aligner size and
word aligner pattern. The word aligner size and word aligner pattern are used in the next two steps.
For example, using a 16-bit PCS/PMA width and a PRBS-23 pattern the corresponding word aligner
size is 3’b101 and word aligner pattern is 0x00007FFFFF.
5. Perform a read-modify-write to the
Word Aligner Size
field (offset 0xA1, bits[10:8]) to change the
word aligner size.
6. Because the word aligner pattern is specified in three separate register fields, to change the word
aligner pattern, you must perform read-modify-writes to the following three register fields:
a.
Word Aligner Pattern
, bits [39:32] (offset 0xA1, bits [7:0] )
b.
Word Aligner Pattern
, bits [31:16] (offset 0xA2, bits [15:0])
c.
Word Aligner Pattern
, bits [15:0] (offset 0xA2, bits [15:0])
7. To enable the PRBS verifier, perform the following three read-modify-write operations to set the
values of these bits to 0:
16-46
Pattern Generators for the Stratix V and Arria V GZ Native PHYs
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview