Altera Transceiver PHY IP Core - Manual (Page 109)

SDC Timing Constraints
The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP
apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V
Native PHY for details.
Related Information
SDC Timing Constraints of Stratix V Native PHY on page 12-74
This section describes SDC examples and approaches to identify false timing paths.
Acronyms
This table defines some commonly used Ethernet acronyms.
Table 4-23: Ethernet Acronyms
Acronym Definition
AN Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.
BER Bit Error Rate.
DME Differential Manchester Encoding.
FEC Forward error correction.
GMII Gigabit Media Independent Interface.
KR Short hand notation for Backplane Ethernet with 64b/66b encoding.
LD Local Device.
LT Link training in backplane Ethernet Clause 72 for 10GBASE-KR and
40GBASE-KR4.
LP Link partner, to which the LD is connected.
MAC Media Access Control.
MII Media independent interface.
OSI Open System Interconnection.
PCS Physical Coding Sublayer.
PHY Physical Layer in OSI 7-layer architecture, also in Altera device scope is: PCS
+ PMA.
PMA Physical Medium Attachment.
PMD Physical Medium Dependent.
SGMII Serial Gigabit Media Independent Interface.
WAN Wide Area Network.
XAUI 10 Gigabit Attachment Unit Interface.
UG-01080
2015.01.19
SDC Timing Constraints 4-53
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option Altera Corporation
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