Altera Transceiver PHY IP Core - Manual (Page 187)

Why Transceiver Dynamic Reconfiguration
Dynamic reconfiguration is necessary to calibrate transceivers to compensate for variations due to PVT.
As silicon progresses towards smaller process nodes, circuit performance is affected more by variations
due to process, voltage, and temperature (PVT). These process variations result in analog voltages that can
be offset from required ranges. Dynamic reconfiguration calibrates transceivers to compensate for
variations due to PVT,
Each channel and each TX PLL have separate dynamic reconfiguration interfaces. The MegaWizard Plug-
In Manager provides informational messages on the connectivity of these interfaces. The following
example shows the messages for a 4-channel Interlaken PHY IP Core.
Example 7-1: Informational Messages for the Transceiver Reconfiguration Interface
PHY IP will require 5 reconfiguration interfaces for connection to the
external reconfiguration controller.
Reconfiguration interface offsets 0-3 are connected to the transceiver
channels.
Reconfiguration interface offset 4 is connected to the transmit PLL.
Although you must initially create a separate reconfiguration interface for each channel and TX PLL in
your design, when the Quartus II software compiles your design, it reduces the number of reconfiguration
interfaces by merging reconfiguration interfaces. The synthesized design typically includes a reconfigura‐
tion interface for at least three channels because three channels share an Avalon-MM slave interface
which connects to the Transceiver Reconfiguration Controller IP Core. Conversely, you cannot connect
the three channels that share an Avalon-MM interface to different Transceiver Reconfiguration
Controller IP cores. Doing so causes a Fitter error. For more information, refer to “Transceiver Reconfi‐
guration Controller to PHY IP Connectivity” .
Dynamic Transceiver Reconfiguration Interface
This section describes the signals in the reconfiguration interface. This interface uses the Avalon-MM
PHY Management interface clock.
Table 7-11: Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [(
70)-1:0]
Input Reconfiguration signals from the Transceiver Reconfiguration
Controller. <
n
> grows linearly with the number of reconfigura‐
tion interfaces. <
n
> initially includes the total number
transceiver channels and TX PLLs before optimization/
merging.
7-20 Why Transceiver Dynamic Reconfiguration
UG-01080
2015.01.19
Altera Corporation Interlaken PHY IP Core
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