Altera Transceiver PHY IP Core - Manual (Page 267)

Controller IP Cores. Doing so causes a Fitter error. For more information, refer to Transceiver Reconfigu‐
ration Controller to PHY IP Connectivity.
The following table describes the signals in the reconfiguration interface. This interface uses a clock
provided by the reconfiguration controller.
Table 10-14: Reconfiguration Interface
Signal Name Direction Description
reconfig_to_xcvr [(70)-1:0]
Input Reconfiguration signals from the
Transceiver Reconfiguration Controller.
grows linearly with the number of
reconfiguration interfaces.
reconfig_from_xcvr [(46)-1:0]
Output Reconfiguration signals to the Transceiver
Reconfiguration Controller. grows
linearly with the number of reconfiguration
interfaces.
If you are using ×6 or ×N bonding, transceiver dynamic reconfiguration requires that you assign the
starting channel number. Logical channel 0 should be assigned to either physical transceiver channel 1 or
channel 4 of a transceiver bank. However, if you have already created a PCB with a different lane
assignment for logical lane 0, you can use the workaound shown in The following example to remove this
restriction. This example redefines the
pma_bonding_master
parameter using the Quartus II Assignment
Editor. In this example, the
pma_bonding_master
was originally assigned to physical channel 1. (The
original assignment could also have been to physical channel 4.) The
to
parameter reassigns the
pma_bonding_master
to the Low Latency PHY instance name. You must substitute the instance name
from your design for the instance name shown in quotation marks.
Example 10-2: Overriding Logical Channel 0 Channel Assignment Restrictions in Stratix V
Devices for ×6 or ×N Bonding
set_parameter -name pma_bonding_master "\"1\"" -to "
|altera_xcvr_low_latency_phy:my_low_latency_phy_inst|sv_xcvr_low_latency_phy_nr:
sv_xcvr_low_latency_phy_nr_inst|sv_xcvr_10g_custom_native:sv_xcvr_10g_custom_native_inst
|sv_xcvr_native:sv_xcvr_native_insts[0].gen_bonded_group_native.sv_xcvr_native_inst"
SDC Timing Constraints
The SDC timing constraints and approaches to identify false paths listed for Stratix V Native PHY IP
apply to all other transceiver PHYs listed in this user guide. Refer to SDC Timing Constraints of Stratix V
Native PHY for details.
10-20 SDC Timing Constraints
UG-01080
2015.01.19
Altera Corporation Low Latency PHY IP Core
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