Altera Transceiver PHY IP Core - Manual (Page 298)

Related Information
SDC Timing Constraints of Stratix V Native PHY on page 12-74
This section describes SDC examples and approaches to identify false timing paths.
Simulation Files and Example Testbench for Deterministic Latency PHY
This section describes simulation file requirements for the Deterministic Latency PHY IP core.
Refer to Running a Simulation Testbench for a description of the directories and files that the Quartus II
software creates automatically when you generate your Deterministic Latency PHY IP Core.
Related Information
Running a Simulation Testbench
11-30 Simulation Files and Example Testbench for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation Deterministic Latency PHY IP Core
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