Xcvr_rx_sd_on, Xcvr_rx_sd_threshold – Altera Transceiver PHY IP Core User Manual
Page 625
Description
Number of parallel cycles to wait before the signal detect block declares loss of signal. Only used for the
PCIe PIPE PHY, SATA, and SAS protocols.
Options
0–29
1
Assign To
Pin - RX serial data
XCVR_RX_SD_ON
Pin Planner and Assignment Editor Name
Receiver Cycle Count Before Signal Detect Block Declares Presence Of Signal
Description
Number of parallel cycles to wait before the signal detect block declares presence of signal. Only used for
the PCIe PIPE PHY, SATA, and SAS protocols.
Options
0–16
1
Assign To
Pin - RX serial data
XCVR_RX_SD_THRESHOLD
Pin Planner and Assignment Editor Name
Receiver Signal Detection Voltage Threshold
Description
Specifies signal detection voltage threshold level, V
th
. The following encodings are defined:
• SDLV_50MV=7
• SDLV_45MV=6
• SDLV_40MV=5
• SDLV_35MV=4
• SDLV_30MV=3
• SDLV_25MV=2
• SDLV_20MV=1
• SDLV_15MV=0
For the PCIe PIPE PHY, SATA, and SAS protocols.
UG-01080
2015.01.19
XCVR_RX_SD_ON
19-31
Analog Parameters Set Using QSF Assignments
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)