Embedded processor interface signals, Embedded processor interface signals -28 – Altera Transceiver PHY IP Core User Manual
Page 84
Table 4-15: Daisy Chain Interface Signals
Signal Name
Direction
Description
dmi_mode_en
Input
When asserted, enable Daisy Chain mode.
dmi_frame_lock
Input
When asserted, the daisy chain state machine has
locked to the training frames.
dmi_rmt_rx_ready
Input
Corresponds to bit 15 of Status report field. When
asserted, the remote receiver.
dmi_lcl_coefl[5:0]
Input
Local update low bits[5:0]. In daisy-chained
configurations, the local update coefficients
substitute for the coefficients that would be set
using Link Training.
dmi_lcl_coefh[1:0]
Input
Local update high bits[13:12]. In daisy-chained
configurations, the local update coefficients
substitute for the coefficients that would be set
using Link Training.
dmi_lcl_upd_new
Input
When asserted, indicates a local update has
occurred.
dmi_rx_trained
Input
When asserted, indicates that the state machine has
finished local training.
dmo_frame_lock
Output
When asserted, indicates that the state machine has
locked to the training frames.
dmo_rmt_rx_ready
Output
Corresponds to the link partner's remote receiver
ready bit.
dmo_lcl_coefl[5:0]
Output
Local update low bits[5:0]. In daisy-chained
configurations, the local update coefficients
substitute for the coefficients that would be set
using Link Training.
dmo_lcl_coefh[1:0]
Output
Local update high bits[13:12]. In daisy-chained
configurations, the local update coefficients
substitute for the coefficients that would be set
using Link Training.
dmo_lcl_upd_new
Output
When asserted, indicates a local update has
occurred.
dmo_rx_trained
Output
When asserted, indicates that the state machine has
finished local training.
Embedded Processor Interface Signals
The optional embedded processor interface signals allow you to use the embedded processor mode of
Link Training. This mode overrides the TX adaptation algorithm and allows an embedded processor to
initialize the link.
4-28
Embedded Processor Interface Signals
UG-01080
2015.01.19
Altera Corporation
Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option