Altera Transceiver PHY IP Core User Manual
Page 528
Table 16-7: Reconfiguration Management Interface
Signal Name
Direction
Description
mgmt_clk_clk
Input
Avalon-MM clock input. The frequency range for the
mgmt_
clk_clk
is 100-125 MHz for Stratix V and Arria V GZ
devices. It is 75-125 MHz for Arria V devices. For Cyclone
V devices, the frequency range is 75-125MHz if the Cyclone
V Hard IP for PCI Express IP Core is not enabled. When the
Hard IP for PCI Express is enabled, the frequency range is
75-100 MHz. Falling outside of the required frequency
range may reduce the accuracy of the calibration functions.
If your design includes the following components:
• The Stratix V Hard IP for PCI Express with CvP enabled
• Any additional transceiver PHY connected to the same
Transceiver Reconfiguration Controller
then you must connect the PLL reference clock which is
called refclk in the Stratix V Hard IP for PCI Express IP
Core to the mgmt_clk_clk signal of the Transceiver Reconfi‐
guration Controller and the additional transceiver PHY. In
addition, if your design includes more than one Transceiver
Reconfiguration Controllers on the same side of the FPGA,
they all must share the mgmt_clk_clk signal.
Note: The frequency range depends on the device speed
grade. Slower speed grade variants of Stratix V
and Arria V GZ devices may require a 100 MHz
reconfiguration clock to close timing.
mgmt_rst_reset
Input
This signal resets the Transceiver Reconfiguration
Controller. This signal is active high and level sensitive.
If the Transceiver Reconfiguration Controller IP Core
connects to an Interlaken PHY IP Core, the Reconfiguration
Controller IP Core
mgmt_rst_reset
must be simultane‐
ously asserted with
phy_mgmt_clk_reset
to bring the
Frame Generators in the link into alignment. Failure to
meet to this requirement will result in excessive transmit
lane-to-lane skew in the Interlaken link.
reconfig_mgmt_
address[6:0]
Input
Avalon-MM address.
reconfig_mgmt_
writedata[31:0]
Input
Input data.
reconfig_mgmt_
readdata[31:0]
Output
Output data.
reconfig_mgmt_write
Input
Write signal. Active high.
UG-01080
2015.01.19
Reconfiguration Management Interface
16-11
Transceiver Reconfiguration Controller IP Core Overview
Altera Corporation