Altera Transceiver PHY IP Core - Manual (Page 163)

Word Addr Bits R/W Register Name Description
0x086
[31:8] - Reserved -
[7:4]
R,
sticky
phase_comp_fifo_error[3:0] Indicates a RX phase compensation FIFO
overflow or
underrun
condition on the
corresponding lane. Reading the value of the
phase_comp_fifo_error
register clears the
bits. This register is only available in the
hard XAUI implementation
From block: RX phase compensation FIFO.
[3:0]
rlv[3:0] Indicates a run length violation. Asserted if
the number of consecutive 1s or 0s exceeds
the number that was set in the Runlength
check option. Bits 0-3 correspond to lanes 0-
3, respectively. Reading the value of the RLV
register clears the bits. This register is only
available in the hard XAUI implementation.
From block: Word aligner.
0x087
[31:16] - Reserved -
[15:8]
R,
sticky
rmfifodatainserted[7:0] When asserted, indicates that the RX rate
match block inserted a ||R|| column. Goes
high for one clock cycle per inserted ||R||
column. Reading the value of the
rmfifoda-
tainserted
register clears the bits. This
register is only available in the hard XAUI
implementation.
From block: Rate match FIFO.
[7:0]
rmfifodatadeleted[7:0] When asserted, indicates that the rate match
block has deleted an ||R|| column. The flag
goes high for one clock cycle per deleted ||
R|| column. There are 2 bits for each lane.
Reading the value of the
rmfifodatade-
leted
register clears the bits. This register is
only available in the hard XAUI implemen‐
tation.
From block: Rate match FIFO.
UG-01080
2015.01.19
XAUI PHY Register Interface and Register Descriptions 6-23
XAUI PHY IP Core Altera Corporation
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