Altera Transceiver PHY IP Core User Manual
Page 666
Chapter
Document
Version
Changes Made
Transceiver PHY
Reset Controller IP
Core
2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Changed the device family support to final in Table 17-1: Device
Family Support.
• Added description for
rx_analogreset
signal in Transceiver
PHY Reset Controller Interfaces section.
Transceiver PLL IP
Core for Stratix V,
Arria V, and Arria V
GZ Devices
2.7
Made the following changes:
• Updated the chapter to indicate new IP instantiation flow using
the IP Catalog.
• Added a note to indicate that it is recommended to use fractional
PLL in fractional mode as a TX PLL or for PLL cascading.
Analog Parameters Set
Using QSF
Assignments
2.7
Made the following changes:
• Removed references to SATA protocol from
XCVR_ANALOG_
PROTOCOL QSF
assignment.
• Added a note related to data rate restriction for
XCVR_RX_
BYPASS_EQ_STAGES_234
assignment.
Revision History for Previous Releases of the Transceiver PHY IP Core
This section provides the revision history for the chapters in this user guide.
Chapter
Document
Version
Changes Made
10GBASE-R PHY IP
Core
2.6
Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
21-6
Revision History for Previous Releases of the Transceiver PHY IP Core
UG-01080
2015.01.19
Altera Corporation
Additional Information for the Transceiver PHY IP Core