Altera Transceiver PHY IP Core User Manual
Page 294
Word Addr
Bits
R/W
Register Name
Description
0x067
[31:0]
RO
pma_rx_is_lockedtoref
When asserted, indicates that the RX
CDR PLL is locked to the reference
clock. Bit < n> corresponds to
channel < n>.
PCS
0x080
[31:0]
RW
Lane or group number
Specifies lane or group number for
indirect addressing, which is used for
all PCS control and status registers.
For variants that stripe data across
multiple lanes, this is the logical
group number. For non-bonded
applications, this is the logical lane
number.
0x081
[31:6]
R
pcs8g_rx_status
Reserved.
[5:1]
R
rx_
bitslipboundaryselect
out
This is an output from the bit slip
word aligner which shows the
number of bits slipped. From block:
Word aligner.
[0]
R
Reserved.
-
0x082
[31:1]
R
pcs8g_tx_status
Reserved.
[0]
RW
Reserved
-
0x083
[31:6]
RW
pcs8g_tx_control
Reserved.
[5:1]
RW
tx_bitslipboundary_
select
Sets the number of bits that the TX
bit slipper needs to slip. To block:
Word aligner.
[0]
RW
tx_invpolarity
When set, the TX interface inverts
the polarity of the TX data. To block:
8B/10B encoder.
0x084
[31:1]
RW
Reserved.
-
[0]
RW
rx_invpolarity
When set, the RX channels inverts
the polarity of the received data. To
block: 8B/10B decoder.
11-26
Register Interface and Descriptions for Deterministic Latency PHY
UG-01080
2015.01.19
Altera Corporation
Deterministic Latency PHY IP Core