Altera Transceiver PHY IP Core User Manual
Page 225
Table 9-9: Byte Order Options
Name
Value
Description
Enable byte ordering block
On/Off
Turn this option on if your application uses
serialization to create a datapath that is larger
than 1 symbol. This option is only available if
you use the byte deserializer for the following
configurations:
• Configuration 1:
• 16-bit FPGA fabric-transceiver
interface
• No 8B/10B decoder (8-bit PMA-PCS
interface)
• Word aligner in manual alignment
mode
• Configuration 2:
• 16-bit FPGA fabric-transceiver
interface
• 8B/10B decoder (10-bit PMA-PCS
interface)
• Word aligner in automatic synchroni‐
zation state machine mode
• Configuration 3:
• 32-bit FPGA fabric-transceiver
interface
• No 8B/10B decoder (16-bit PMA-PCS
interface)
• Word aligner in manual alignment
mode
• Configuration 4:
• 32-bit FPGA fabric-transceiver
interface
• 8B/10B decoder (20-bit PMA-PCS
interface)
• Word aligner in manual alignment
mode
• Configuration 5:
• 40-bit FPGA fabric-transceiver
interface
• No 8B/10B decoder (20-bit PMA-PCS
interface)
• Word aligner in manual alignment
mode
This option creates the
rx_byteordflag
signal which is asserted when the received
data is aligned to the byte order pattern that
you specified.
9-12
Byte Order Parameters
UG-01080
2015.01.19
Altera Corporation
Custom PHY IP Core